As integrated circuits are produced with greater and greater levels of circuit density, efficient testing schemes that guarantee very high fault coverage while minimizing test costs and chip area overhead have become essential. However, as the complexity of circuits continues to increase, high fault coverage of several types of fault models becomes more difficult to achieve with traditional testing paradigms. This difficulty arises for several reasons. First, larger integrated circuits have a very high and still increasing logic-to-pin ratio that creates a test data transfer bottleneck at the chip pins. In addition, larger circuits require a prohibitively large volume of test data that must be then stored in external testing equipment. Moreover, applying the test data to a large circuit requires an increasingly long test application time. Furthermore, present external testing equipment is unable to test such larger circuits at their speed of operation.
Integrated circuits are presently tested using a number of structured design for testability (DFT) techniques. These techniques rest on the general concept of making all or some state variables (memory elements like flip-flops and latches) directly controllable and observable. If this can be arranged, a circuit can be treated, as far as testing of combinational faults is concerned, as a combinational or a nearly combinational network. The most-often used DFT methodology is based on scan chains. It assumes that during testing all (or almost all) memory elements are connected into one or more shift registers. A circuit that has been designed for test has two modes of operation: a normal mode and a test, or scan, mode. In the normal mode, the memory elements perform their regular functions. In the scan mode, the memory elements become scan cells that are connected to form a number of shift registers called scan chains. These scan chains are used to shift a set of test patterns into the circuit and to shift out circuit, or test, responses to the test patterns. The test responses are then compared to fault-free responses to determine if the circuit under test works properly.
Some of the DFT techniques include compactors to compress the test responses from the scan chains. FIG. 1 is a schematic diagram illustrating a prior art compactor being used to reduce a size of scan response. The maximum compaction may be achieved if the compactor is a finite-state machine (FSM), and the result of compaction is read once for a test vector or even after the whole set of test vectors. If the test response is completely deterministic, then there is a single correct final state of the FSM, and all other states correspond to faults. Increasing the number of FSM's states may rapidly reduce the probability of undetected faults and make it possible to distinguish among different faults.
The situation deteriorates if part of the test response bits are for some reason unknown (i.e., having unknown values or X-values). Each X-value may double the number of final legal states of the FSM. If the number of X-values reaches the number of flip-flops inside the FSM, then the final state may provide little information. To solve this problem, one of the following two approaches is usually used: X-tolerant compaction or pre-compaction (or pre-compression) masking.
Schemes with X-tolerant compaction may have the same configuration as shown in FIG. 1, except output values are observed more frequently (typically after each data shifting in scan chains). The compactor module is either a combinational circuit (e.g., in X-compact technique, see Subhasish Mitra and Kee Sup Kim, X-compact: an efficient response compaction technique for test cost reduction, ITC International Test Conference, 2002, paper 11.2, pp. 311–320; Subhasish Mitra and Kee Sup Kim, X-compact: an efficient response compaction technique, IEEE Trans. on CAD of IC and Systems, 2004, vol. 23, No. 3, pp. 421–432; and Subhasish Mitra and Kee Sup Kim, Compacting circuit responses, U.S. Patent Application Publication No. 2003/0188269, Oct. 2, 2003), or a finite-state machine (FSM) with finite impulse response (e.g., in the convolutional compaction technique, see Janusz Rajski, Jerzy Tyszer, Chen Wang and Sudhakar M. Reddy, Convolutional compaction of test responses, ITC International Test Conference, 2003, paper 29.3, pp. 745–754). One basic idea behind these two X-tolerant compaction approaches is as follows: if each scan out bit participates in multiple checksums, then X-value of another bit may probably destroy only part of these checksums, whereas the remaining checksums may continue to support observability of the scan out bit and detectability of corresponding faults of the design under test.
The pre-compaction masking approach works based on the following principle: if a particular scan out bit is known to be an X-value at a particular moment, then before compaction the X-value may be masked, e.g., via ANDing with external mask inputs (see FIG. 2 and Benoit Nadeau-Dostie, Method of masking corrupt bits during signature analysis and circuit for use therewith, U.S. Pat. No. 6,745,359, issued Jun. 1, 2004). After masking, all signals are fully deterministic, and a compactor may be used for compression. Since the total size of masks is huge (the same as the total size of all scan chains), the masks conventionally have to be compressed. However, such compression either requires complicated decoding and extra on-chip memory, or produces masking of “good” scan out bits (when, for example, the whole scan chain is masked out). Thus, to solve the foregoing-described problems, it is desirable to provide a new scheme to implement test output compression.